An aspect of the present invention relates to data processing systems, and in particular, to verifying the functionality of an integrated circuit by using data modification.
Hardware components like a chip may act as a bridge between two different interfaces. Such a component may continuously receive data packets via a source interface to store them in a host memory via a second interface. The address of each of the incoming data packets at the source interface is translated to a physical address on the host memory. In most of the cases, address translation mechanisms are based on scatter-gather lists. These lists are used for storing the locations of the data packets in the host memory and for describing how the request is placed in the host memory. If there is any error detected on any of the data packets received on the source interface, that data packet should be discarded and should not be sent to the host side.
Correct operation of such a chip can be checked by verifying whether it is dropping the erroneous packets and not sending them to the host memory. This is done in current methods by using information stored in an address translation table, and by a bookkeeping of the number of packets on the source side. The software based on this translation-table testing approach tends to be cumbersome and complex.